I work right in the sweet spot where hardware meets software. I write low-level firmware, device drivers, and kernel code for RISC-V systems. My work spans from bare-metal to RTOSes, microkernels, Linux kernel to OSes, and I enjoy the challenge of making new hardware production-ready.
Lately, I've been building agentic AI systems, named 'ATESOR' which automates the the RISC-V software porting.
Experience
Sr. Engineer - 10xEngineers
· Lahore, PK
Leading strategic collaboration with the Eclipse Foundation to architect and scale RISC-V support for the Eclipse ThreadX RTOS, by driving architectural clean-ups, feature work, and long-term maintainability for both RV64 and RV32 ports.
Wrote RV32/gnu port for Eclipse ThreadX along with its QEMU-virt BSP. Later wrote BSP of BananaPi BPI-F3 (SpacemiT K1) board for ThreadX.
Enabled seL4 microkernel support for SpacemiT's BananaPi BPI-F3 by implementing low-level kernel init, peripheral drivers (UART, Timer, …), and validated with the full seL4 test suite 100% pass rate.
Leading maintenance and horizontal scaling of Cloud-V (RISC-V CI Services Platform) 97.6% uptime, 120+ global users across diverse CI pipelines.
Benchmarked RISC-V SBCs from SiFive, SpacemiT, and StarFive with SPEC, CoreMark, and Phoronix published 10+ comparison reports on Cloud-V to give the community data-driven board-selection insights.
Software Engineer II - Xcelerium Inc.
· California, USA
Built the custom BSP for Xcelerium's RISC-V64 core in Zephyr RTOS and also enabled proprietary RISC-V instructions including the Vector Extension in it.
Led the “Linux Boot” project successfully booted Linux Kernel v6.10 on Xcelerium's SW simulator (Hydra VP) and Scalar Core (Hydra Tile SU).
Built a Sequence Pytest framework for verifying a RISC-V Vector processor with RVV 1.0 + Xcelerium's proprietary instructions.
Contributed RVV cryptography instructions to the SW RISC-V simulator to support RVV Crypto Extension v1.0.0.
Engineered a high-perf AWS verification suite integrated with FPGA + DUT memory maps; refactored data transfer from 8-bit to 64-bit widths resulting 700% load/store throughput increase.
Committer - Eclipse ThreadX (Eclipse Foundation)
· Open Source
I'm Official committer at Eclipse ThreadX under Eclipse Foundation, responsible for maintaining, reviewing and merging changes across RV64 and RV32 ports codebase.
See status Here : https://projects.eclipse.org/projects/iot.threadx/CM/akifejaz
See maintainer status: https://docs.sel4.systems/Hardware/bananapi-f3.html
Contributor - Linux Kernel
· Upstream
Upstream patch merged in v6.20 SPI subsystem: `spi: cadence-qspi` (drivers/spi/spi-cadence-quadspi.c) and stable-backported into the 6.19.4 series.
Working in the RISC-V corner of mainline alongside the 10xEngineers kernel team, StarFive pinctrl, Cadence QSPI, and board bring-up for RISC-V SBCs targeting v6.19 / v6.20.
Prior: booted Linux Kernel v6.10 on Xcelerium's RISC-V SW simulator (Hydra VP) and Scalar Core (Hydra Tile SU) during my time at Xcelerium.
Education
B.S. Computer Engineering (BSCE) - Information Technology University (ITU)
· CGPA 3.76 / 4.00, focus on OS/systems, embedded, and computer architecture.
Open-source multi-stage framework that ports software to RISC-V automatically. It uses LangGraph agents, Docker containers, and native RISC-V test environments.
Added and now officially maintain BananaPi BPI-F3 board support in the seL4 microkernel: kernel init, peripheral drivers, and a 100% seL4-test pass rate.
Assistants agree with your premise instead of the specification. Grounding every answer in the ratified specs and the RISC-V Unified Database fixes it.
Instruction Set Architecture, Assembly Language, RISC-V, Community
Frequently asked questions
Who is Akif Ejaz?
Akif Ejaz is a Senior Systems and Firmware Engineer. He works at 10xEngineers in Lahore, PK. He writes firmware, device drivers, and kernel code for RISC-V Systems.
What does Akif Ejaz work on?
Akif Ejaz works on RISC-V software enablement. He writes low-level firmware, device drivers, and kernel code. His work covers bare-metal systems, real-time operating systems, microkernels, and the Linux kernel. He holds the role of Senior Engineer at 10xEngineers since Mar 2025.
Which open-source projects does Akif Ejaz maintain?
Akif Ejaz works on 3 open-source projects. He is a Committer for Eclipse ThreadX (Eclipse Foundation) from Feb 2026. He is a Maintainer for seL4 Microkernel from Dec 2025. He is a Contributor for Linux Kernel from 2025.
What is ATESOR?
ATESOR is an open-source framework that ports software to RISC-V automatically. Akif Ejaz built it. The framework uses LangGraph agents, Docker containers, and native RISC-V test machines.
What certifications does Akif Ejaz hold?
Akif Ejaz holds 4 certifications from The Linux Foundation. He completed LFD114: Porting Software to RISC-V in Apr 2026. He completed LFD123: Open Source RT-Thread RTOS on RISC-V in Jul 2025. He completed LFD103: A Beginner's Guide to Linux Kernel Development in Jul 2025. He completed LFD110: Introduction to RISC-V in Dec 2024.
Has Akif Ejaz published research?
Yes. Akif Ejaz published 5 papers and articles. His most recent paper is "Beyond the Basics: Elevating Eclipse ThreadX to a First-Class RTOS for RISC-V". It appeared at RISC-V Summit EU '2026 in Apr 2026.
Is Akif Ejaz available for collaboration or hire?
Akif Ejaz is open to collaborations. He works from Lahore, PK. You can find his contact details at https://akifejaz.dev.